1、TheDescriptionofAT89S511GeneralDescriptionTheAT89S51isalow-power/high-performanceCMOS8-bitmicrocontrollerwith4KbytesofIn-SystemProgrammableFlashmemory/ThedeviceismanufacturedusingAtmelshigh-densitynonvolatilememorytechnologyandiscompatiblewiththeindus-try-standard80C51instructionsetandpinout/Theon-c
2、hipFlashallowstheprogrammemorytobereprogrammedin-systemorbyaconventionalnonvolatilememorypro-grammer/Bycombiningaversatile8-bitCPUwithIn-SystemProgrammableFlashonamonolithicchip/theAtmelAT89S51isapowerfulmicrocontrollerwhichprovidesahighly-flexibleandcost-effectivesolutiontomanyembeddedcontrolapplic
3、ations/TheAT89S51providesthefollowingstandardfeatures/4KbytesofFlash/128bytesofRAM/32I/Olines/Watchdogtimer/twodatapointers/two16-bittimer/counters/afive-vectortwo-levelinterruptarchitecture/afullduplexserialport/on-chiposcillator/andclockcircuitry/Inaddition/theAT89S51isdesignedwithstaticlogicforop
4、erationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes/TheIdleModestopstheCPUwhileallowingtheRAM/timer/counters/serialport/andinterruptsystemtocontinuefunctioning/ThePower-downmodesavestheRAMcon-tentsbutfreezestheoscillator/disablingallotherchipfunctionsuntilthenextexternalinterr
5、uptorhardwarereset/2PortsPort0isan8-bitopendrainbi-directionalI/Oport/Asanoutputport/eachpincansinkeightTTLinputs/When1sarewrittentoport0pins/thepinscanbeusedashigh-impedanceinputs/Port0canalsobeconfiguredtobethemultiplexedlow-orderaddress/databusduringaccessestoexternalprogramanddatamemory/Inthismo
6、de/P0hasinternalpull-ups/Port0alsoreceivesthecodebytesduringFlashprogrammingandoutputsthecodebytesdur-ingprogramverification/Externalpull-upsarerequiredduringprogramverification/Port1isan8-bitbi-directionalI/Oportwithinternalpull-ups/ThePort1outputbufferscansink/sourcefourTTLinputs/When1sarewrittent
7、oPort1pins/theyarepulledhighbytheinter-nalpull-upsandcanbeusedasinputs/Asinputs/Port1pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpull-ups/Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification/Port2isan8-bitbi-directionalI/Oportwithinternalpul
8、l-ups/ThePort2outputbufferscansink/sourcefourTTLinputs/When1sarewrittentoPort2pins/theyarepulledhighbytheinter-nalpull-upsandcanbeusedasinputs/Asinputs/Port2pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpull-ups/Port2emitsthehigh-orderaddressbyteduringfetchesfromextern
9、alprogrammemoryanddur-ingaccessestoexternaldatamemorythatuse16-bitaddresses(MOVXDPTR)/Inthisapplication/Port2usesstronginternalpull-upswhenemitting1s/Duringaccessestoexternaldatamemorythatuse8-bitaddresses(MOVXRI)/Port2emitsthecontentsoftheP2SpecialFunctionRegister/Port2alsoreceivesthehigh-orderaddr
10、essbitsandsomecontrolsignalsduringFlashprogram-mingandverification/Port3isan8-bitbi-directionalI/Oportwithinternalpull-ups/ThePort3outputbufferscansink/sourcefourTTLinputs/When1sarewrittentoPort3pins/theyarepulledhighbytheinter-nalpull-upsandcanbeusedasinputs/Asinputs/Port3pinsthatareexternallybeing
11、pulledlowwillsourcecurrent(IIL)becauseofthepull-ups/Port3receivessomecontrolsignalsforFlashprogrammingandverification/Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89S51/asshowninthefol-lowingtable/3SpecialFunctionRegistersAmapoftheon-chipmemoryareacalledtheSpecialFunctionRegister(SFR)sp
12、aceisshowninTable5-1/Notethatnotalloftheaddressesareoccupied/andunoccupiedaddressesmaynotbeimple-mentedonthechip/Readaccessestotheseaddresseswillingeneralreturnrandomdata/andwriteaccesseswillhaveanindeterminateeffect/Usersoftwareshouldnotwrite1stotheseunlistedlocations/sincetheymaybeusedinfutureprod
13、uctstoinvokenewfea-tures/Inthatcase/theresetorinactivevaluesofthenewbitswillalwaysbe0/InterruptRegisters/TheindividualinterruptenablebitsareintheIEregister/TwoprioritiescanbesetforeachofthefiveinterruptsourcesintheIPregister/DualDataPointerRegisters/Tofacilitateaccessingbothinternalandexternaldatame
14、mory/twobanksof16-bitDataPointerRegistersareprovided/DP0atSFRaddresslocations82H-83HandDP1at84H-85H/BitDPS=0inSFRAUXR1selectsDP0andDPS=1selectsDP1/TheusershouldALWAYSinitializetheDPSbittotheappropriatevaluebeforeaccessingtherespectiveDataPointerRegister/PowerOffFlag/ThePowerOffFlag(POF)islocatedatbi
15、t4(PCON/4)inthePCONSFR/POFissetto“1”duringpowerup/Itcanbesetandrestundersoftwarecontrolandisnotaffectedbyreset/4MemoryOrganizationMCS-51deviceshaveaseparateaddressspaceforProgramandDataMemory/Upto64KbyteseachofexternalProgramandDataMemorycanbeaddressed/4/1ProgramMemoryIftheEApinisconnectedtoGND/allp
16、rogramfetchesaredirectedtoexternalmemory/OntheAT89S51/ifEAisconnectedtoVCC/programfetchestoaddresses0000HthroughFFFHaredirectedtointernalmemoryandfetchestoaddresses1000HthroughFFFFHaredirectedtoexternalmemory/4/2DataMemoryTheAT89S51implements128bytesofon-chipRAM/The128bytesareaccessibleviadirectandi
17、ndirectaddressingmodes/Stackoperationsareexamplesofindirectaddressing/sothe128bytesofdataRAMareavailableasstackspace/7/WatchdogTimer(One-timeEnabledwithReset-out)TheWDTisintendedasarecoverymethodinsituationswheretheCPUmaybesubjectedtosoftwareupsets/TheWDTconsistsofa14-bitcounterandtheWatchdogTimerRe
18、set(WDTRST)SFR/TheWDTisdefaultedtodisablefromexitingreset/ToenabletheWDT/ausermustwrite01EHand0E1HinsequencetotheWDTRSTregister(SFRlocation0A6H)/WhentheWDTisenabled/itwillincrementeverymachinecyclewhiletheoscillatorisrunning/TheWDTtimeoutperiodisdependentontheexternalclockfrequency/Thereisnowaytodis
19、abletheWDTexceptthroughreset(eitherhardwareresetorWDToverflowreset)/WhenWDTover-flows/itwilldriveanoutputRESETHIGHpulseattheRSTpin/5UsingtheWDTToenabletheWDT/ausermustwrite01EHand0E1HinsequencetotheWDTRSTregister(SFRlocation0A6H)/WhentheWDTisenabled/theuserneedstoserviceitbywriting01EHand0E1HtoWDTRS
20、TtoavoidaWDToverflow/The14-bitcounteroverflowswhenitreaches16383(3FFFH)/andthiswillresetthedevice/WhentheWDTisenabled/itwillincrementeverymachinecyclewhiletheoscillatorisrunning/ThismeanstheusermustresettheWDTatleastevery16383machinecycles/ToresettheWDTtheusermustwrite01EHand0E1HtoWDTRST/WDTRSTisawr
21、ite-onlyregister/TheWDTcountercannotbereadorwritten/WhenWDToverflows/itwillgenerateanoutputRESETpulseattheRSTpin/TheRESETpulsedura-tionis98xTOSC/whereTOSC=1/FOSC/TomakethebestuseoftheWDT/itshouldbeservicedinthosesectionsofcodethatwillperiodicallybeexecutedwithinthetimerequiredtopreventaWDTreset/InPo
22、wer-downmodetheoscillatorstops/whichmeanstheWDTalsostops/WhileinPower-downmode/theuserdoesnotneedtoservicetheWDT/TherearetwomethodsofexitingPower-downmode/byahardwareresetorviaalevel-activatedexternalinterrupt/whichisenabledpriortoenteringPower-downmode/WhenPower-downisexitedwithhardwarereset/servic
23、ingtheWDTshouldoccurasitnormallydoeswhenevertheAT89S51isreset/ExitingPower-downwithaninterruptissignificantlydifferent/Theinterruptisheldlowlongenoughfortheoscillatortostabilize/Whentheinterruptisbroughthigh/theinterruptisserviced/TopreventtheWDTfromresettingthedevicewhiletheinterruptpinisheldlow/th
24、eWDTisnotstarteduntiltheinterruptispulledhigh/ItissuggestedthattheWDTberesetduringtheinterruptservicefortheinterruptusedtoexitPower-downmode/ToensurethattheWDTdoesnotoverflowwithinafewstatesofexitingPower-down/itisbesttoresettheWDTjustbeforeenteringPower-downmode/BeforegoingintotheIDLEmode/theWDIDLE
25、bitinSFRAUXRisusedtodeterminewhethertheWDTcontinuestocountifenabled/TheWDTkeepscountingduringIDLE(WDIDLEbit=0)asthedefaultstate/TopreventtheWDTfromresettingtheAT89S51whileinIDLEmode/theusershouldalwayssetupatimerthatwillperiodicallyexitIDLE/servicetheWDT/andreenterIDLEmode/WithWDIDLEbitenabled/theWDTwillstoptocountinIDLEmodeandresumesthecountuponexitfromIDLE/Timer0andTimer1intheAT89S51operatethesamewayasTimer0andTimer1intheAT89C51/Forfurtherinformationonthetimersoperation/pleaseclickonthedocumentlinkbelow/http//
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