1、StructureandfunctionoftheMCS-51seriesStructureandfunctionoftheMCS-51seriesone-chipcomputerMCS-51isanameofapieceofone-chipcomputerserieswhichIntelCompanyproduces/Thiscompanyintroduced8top-gradeone-chipcomputersofMCS-51seriesin1980afterintroducing8one-chipcomputersofMCS-48seriesin1976/Itbelongtoalotof
2、kindsthislineofone-chipcomputerthechipshave/suchas8051/8031/8751/80C51BH/80C31BH/etc//theirbasiccomposition/basicperformanceandinstructionsystemareallthesame/8051dailyrepresentatives-51serialone-chipcomputer/Anone-chipcomputersystemismadeupofseveralfollowingparts/(1)Onemicroprocessorof8(CPU)/(2)Atsl
3、icedatamemoryRAM(128B/256B)/itusedtodepositingnotcanreading/datathatwrite/suchasresultnotmiddleofoperation/finalresultanddatawantedtoshow/etc/(3)ProcedurememoryROM/EPROM(4KB/8KB)/isusedtopreservetheprocedure/someinitialdataandforminslice/ButdoesnottakeROM/EPROMwithinsomeone-chipcomputers/suchas8031/
4、8032/80C/etc/(4)Four8runsidebysideI/OinterfaceP0fourP3/eachmouthcanuseasintroduction/mayuseasexportingtoo/(5)Twotimer/counter/eachtimer/countermaysetupandcountintheway/usedtocounttotheexternalincident/cansetupintoatimingwaytoo/andcanaccordingtocountorresultoftimingrealizethecontrolofthecomputer/(6)F
5、ivecutoffcuttingoffthecontrolsystemofthesource/(7)OneallduplexserialI/OmouthofUART(universalasynchronousreceiver/transmitter(UART)/isitrealizeone-chipcomputerorone-chipcomputerandserialcommunicationofcomputertousefor/(8)Stretchoscillatorandclockproducecircuit/quartzcrystalfinelytuneelectriccapacityn
6、eedouter/Allowoscillationfrequencyas12nowatmost/Everytheabove-mentionedpartwasjoinedthroughtheinsidedatabus/Amongthem/CPUisacoreoftheone-chipcomputer/itisthecontrolofthecomputerandcommandcentre/madeupofsuchpartsasarithmeticunitandcontroller/etc/Thearithmeticunitcancarryon8personsofarithmeticoperatio
7、nandunitALUoflogicoperationwhileincludingone/the1storingdevicetemporarilyof8/storingdevice2temporarily/8saccumulationdeviceACC/registerBandprocedurestateregisterPSW/etc/PersonwhoaccumulateACCcountby2inputendsenteredofcheckingetc/temporarilyasoneoperationoften/comefrompersonwhostore1operationisitisit
8、makeoperationtogoontocounttemporarily/operationresultandloopbackACCwithanotherone/Inaddition/ACCisoftenregardedasthetransferstationofdatatransmissionon8051inside/Thesameasgeneralmicroprocessor/itisthebusiestregister/HelprememberingthatagreeingwithAexpressesintheorder/Thecontrollerincludestheprocedur
9、ecounter/theorderisdeposited/theorderdecipher/theoscillatorandtimingcircuit/etc/Theprocedurecounterismadeupofcounterof8fortwo/amountsto16/Itisabyteaddresscounteroftheprocedureinfact/thecontentisthenextIAthatwillcarriedoutinPC/Thecontentwhichchangesitcanchangethedirectionthattheprocedurecarriesout/Sh
10、akethecircuitin8051one-chipcomputers/onlyneedouterquartzcrystalandfrequencytofinelytunetheelectriccapacity/itsfrequencyrangeisits12MHZof1/2MHZ/Thispulsesignal/as8051basicbeatsofworking/namelytheminimumunitoftime/8051isthesameasothercomputers/theworkinharmonyunderthecontrolofthebasicbeat/justlikeanor
11、chestraaccordingtothebeatplaythatiscommanded/ThereareROM(procedurememory/canonlyread)andRAMin8051slices(datamemory/canisitcanwrite)twotoread/theyhaveeachindependentmemoryaddressspace/disposewaytobethesamewithgeneralmemoryofcomputer/Procedure8051memoryand8751sliceprocedurememorycapacity4KB/addressbeg
12、infrom0000H/usedforpreservingtheprocedureandformconstant/Data8051-87518031ofmemorydatamemory128B/addressfalse00FH/useformiddleresulttodepositoperation/thedataarestoredtemporarilyandthedataarebufferedetc/InRAMofthis128B/thereisunitof32bytesthatcanbeappointedasthejobregister/thisandgeneralmicroprocess
13、orisdifferent/8051sliceRAMandjobregisterrankoneformationthesametoarrangethelocation/ItisnotverythesamethatthememoryofMCS-51seriesone-chipcomputerandgeneralcomputerdisposesthewayinaddition/Generalcomputerforfirstaddressspace/ROMandRAMcanarrangeindifferentspacewithintherangeofthisaddressatwill/namelyt
14、headdressesofROMandRAM/withdistributingdifferentaddressspaceinaformation/Whilevisitingthememory/correspondingandonlyanaddressMemoryunit/canROM/itcanbeRAMtoo/andbyvisitingtheordersimilarly/ThiskindofmemorystructureiscalledthestructureofPrinceton/8051memoriesaredividedintoprocedurememoryspaceanddatame
15、moryspaceonthephysicsstructure/therearefourmemoryspacesinall/Theprocedurestoresinoneanddatamemoryspaceoutsidedatamemoryandoneinprocedurememoryspaceandoneoutsideone/thestructureformsofthiskindofproceduredeviceanddatamemoryseparatedformdatamemory/calledHarvardstructure/Butusetheanglefromusers/8051memo
16、ryaddressspaceisdividedintothreekinds/(1)Intheslice/arrangeblocksofFFFFH/0000Hoflocation/inunisonoutsidetheslice(use16addresses)/(2)Thedatamemoryaddressspaceoutsideoneof64KB/theaddressisarrangedfrom0000H64KBFFFFH(with16addresses)tootothelocation/(3)Datamemoryaddressspaceof256B(use8addresses)/Threeab
17、ove-mentionedmemoryspaceaddressesoverlap/fordistinguishinganddesigningtheordersymbolofdifferentdatatransmissionintheinstructionsystemof8051/CPUvisitslice/ROMorderspendMOVC/visitblockRAMorderusesMOVXoutsidetheslice/RAMorderusesMOVtovisitinslice/8051one-chipcomputerhavefour8walkabreastI/Oport/callP0/P
18、1/P2andP3/Eachportis8accuratetwo-waymouths/accountsfor32pinsaltogether/EveryoneI/Olinecanbeusedasintroductionandexportedindependently/Eachportincludesalatch(namelyspecialfunctionregister)/oneexportsthedriverandaintroductionbuffer/Makedatacanlatchwhenoutputting/datacanbufferwhenmakingintroduction/but
19、fourfunctionofpasswaytheseself-same/Expandamongthesystemofmemoryoutsidehavingslice/fourportthesemayserveasaccuratetwo-waymouthofI/Oincommonuse/Expandamongthesystemofmemoryoutsidehavingslice/P2mouthseehigh8addressoff；P0mouthisatwo-waybus/sendtheintroductionof8lowaddressesanddata/exportintimesharingTh
20、ecircuitof8051one-chipcomputersandfourI/Oportsisveryingeniousindesign/FamiliarwithI/Oportlogicalcircuit/notonlyhelptouseportscorrectlyandrationally/andwillinspiretodesigningtheperipherallogicalcircuitofone-chipcomputertosomeextent/Loadabilityandinterfaceofporthavecertainrequirement/becauseoutputgrad
21、e/P0ofmouthandP1endoutput/P3ofmouthgradedifferentatstructure/so/theloadabilityandinterfaceofitsdoordemandtohavenothingincommonwitheachother/P0mouthisdifferentfromothermouths/itsoutputgradedrawstheresistancesupreme/Whenusingitasthemouthincommonusetouse/outputgradeisitleakcircuittoturnon/isitisiturgeN
22、MOSdrawtheresistanceontakingtobeouterwithitwhileinputtingtogoouttofail/Whenbeingusedasintroduction/shouldwrite1toalatchfirst/EveryonewithP0mouthcandrive8ModelLSTTLloadtoexport/P1mouthisanaccuratetwo-waymouthtoo/usedasI/Oincommonuse/DifferentfromP0mouthoutputofcircuitits/drawloadresistancelinkwithpow
23、eroninsidehave/Infact/theresistanceisthattwoeffectsareinchargeofFETandtogether/OneFETisinchargeofload/itsresistanceisregular/Anotheronecanisitleadtoworkwithcloseattwostate/makeitsPresidentresistancevaluechangeapproximate0orgroupvalueheavytwosituationvery/Whenitis0thattheresistanceisapproximate/candr
24、awthepintothehighlevelfast；Whenresistancevalueisverylarge/P1mouth/inordertohindertheintroductionstatehigh/OutputasP1mouthhighelectricityatordinarytimes/canisitdrawelectriccurrentloadtoofferoutwards/drawtheresistanceonneedntanswerandthen/Herewhentheportisusedasintroduction/mustwriteinto1tothecorrespo
25、ndinglatchfirsttoo/makeFETend/ThestructureofP2somemouthissimilartoP0mouth/thereareMUXswitches/Isitsimilartomouthpartlytourge/butmouthlargeaconversioncontrolssomethanP1/P3mouthonemulti-functionalport/mouthgettingmanythanP1ithaveand3doorand4buffer/Twopartthese/makeherbesidesaccuratetwo-wayfunctionwith
26、P1mouthjust/canalsousethesecondfunctionofeverypin/anddoor3functiononeswitchinfact/itdeterminestobetooutputdataoflatchtooutputsecondsignaloffunction/ActasW=At1oclock/outputQendsignal；ActasQ=At1oclock/canoutputWlinesignal/Atthetimeofprogramming/itisthatthefirstfunctionisstillthesecondfunctionbutneednt
27、havesoftwarethatsetupP3mouthinadvance/IthardwarenotinsideistheautomatictohavetwofunctionoutputtedwhenCPUcarriesonSFRandseeksthelocation(thelocationorthebyte)tovisittoP3mouth/atnotlastinglining/thereareinsidehardwarelatchQs=1/TheoperationprincipleofP3mouthissimilartoP1mouth/Outputgrade/P3ofmouth/P1of
28、P1/connectwithinsidehaveloadresistanceofdrawing/everyoneoftheycandrive4ModelLSTTLloadtooutput/Aswhileinputtingthemouth/anyTTLorNMOScircuitcandriveP1of8051one-chipcomputersasP3mouthinanormalway/Becausedrawresistanceonoutputgradeofthemhave/canopenawaycollectortooordrain-sourceresistanceisiturgetoopena
29、way/donotneedtohavetheresistanceofdrawingouter/Mouthsareallaccuratetwo-waymouthstoo/Whentheconductisinput/mustwritethecorrespondingportlatchwith1first/Asto80C51one-chipcomputer/portcanonlyoffermilliampereofoutputelectriccurrents/isitoutputmouthgowhenurgingoneordinarybasingoftransistortoregardas/shou
30、ldcontactaresistanceamongtheportandtransistorbase/inordertotheelectricitywhilerestrainingthehighlevelfromexportingP1P3Beingrestoredtothethroneistheoperationofinitializingofanone-chipcomputer/ItsmainfunctionistoturnPCinto0000Hinitially/maketheone-chipcomputerbegintoholdtheconductprocedurefromunit0000
31、H/Exceptthattheonesthatenterthesystemareinitializednormally/asbecauseprocedureoperateitmakemistakesoroperatetherearentmistake/inordertoextricateoneselffromapredicament/needtobepressedandrestoredtothethronethekeyrestartingtoo/Itisaninputendwhichisrestoredtothethronethesignalin8051ChinaRSTpin/Restoretothethronesignalhighlevel
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